As chip scaling approaches its physical limits, performance gains from traditional linewidth reduction are becoming increasingly difficult to achieve. To maintain growth in computing performance and energy efficiency, the industry is turning its gaze toward Advanced Packaging technologies.
By introducing high-density interconnects and 3D stacking between chips, advanced packaging enables high-speed transmission, low power consumption, and high integration without altering the chip architecture. Among them, CoWoS technology is the most representative high-performance packaging solution in recent years, evolving into various forms such as CoPoS and CoWoP, which constitute the main development direction of next-generation packaging technology.
Table of Contents
CoWoS Technology Basis: The Core of 2.5D and 3D Integration
CoWoS (Chip-on-Wafer-on-Substrate) is a high-density packaging architecture centered on the Interposer. Its design concept involves stacking and connecting multiple chips at the wafer level first, and then packaging the entire assembly onto a substrate. This structure shortens signal transmission distances while simultaneously reducing power consumption and system size.
Based on different interposer materials and interconnection methods, CoWoS technology can be categorized into three main types:
- CoWoS-S: Uses a Silicon Interposer, offering the highest interconnect density and integration capability, suitable for High-Performance Computing (HPC) applications.
- CoWoS-R: Replaces the silicon interposer with RDL (Redistribution Layer), reducing process costs and increasing design flexibility.
- CoWoS-L: A hybrid design combining Silicon and RDL, balancing high performance and cost-efficiency, capable of supporting larger chip and memory stacking.
CoWoS-L is regarded as the equilibrium point in existing architectures, capable of breaking through interposer area limitations while maintaining high-speed signal transmission and good thermal performance.
CoPoS: Panel-Level Packaging, Opening the Era of “Square Replacing Round”
As the size of AI and HPC chips continues to grow, the area utilization rate and production capacity of traditional circular wafers are becoming limited. Consequently, the concept of **CoPoS (Chip-on-Panel-on-Substrate)** panel-level packaging has emerged.
CoPoS employs a rectangular “Panel RDL Layer” to replace the circular wafer interposer. Chips can be arranged directly on a rectangular substrate and connected to the underlying substrate through the packaging process. This design not only improves **area utilization and production efficiency** but also integrates chips of different sizes, reducing packaging warpage and yield issues.
Furthermore, panel materials can utilize high-stability media such as glass or sapphire, which helps enhance heat dissipation and reduce warpage.
Current mainstream size directions include specifications like **310×310 mm, 515×510 mm, and 750×620 mm**, gradually pushing the packaging process from “round to square” and becoming a potential mainstream trend in the post-Moore era.
It is worth noting that while CoPoS and **FOPLP (Fan-out Panel Level Packaging)** both belong to panel-level packaging, their market positioning is distinctly different:
- CoPoS is used for the integration of high-performance chips and interposers.
- FOPLP is mostly used for mid-to-low-end applications such as Power Management ICs (PMIC) and RF chips, which do not require an interposer structure.
CoWoP: An Innovative Route to Simplify Packaging Levels
Unlike CoPoS which pursues panelization, the goal of **CoWoP (Chip-on-Wafer-on-Platform PCB)** is to **simplify the packaging hierarchy**. In traditional CoWoS structures, the connection between chips and memory modules to the motherboard requires passing through the interposer, packaging substrate, and BGA solder balls layer by layer, resulting in structural complexity and added costs.
CoWoP eliminates the packaging substrate and BGA, instead using a **Platform PCB** with high-precision interconnection capabilities as the carrier layer, allowing the interposer and chip modules to be **mounted directly onto the PCB**.
This approach shortens signal transmission paths, enhances signal integrity, and improves heat dissipation and power delivery efficiency.
If this technology is successfully mass-produced, it could redefine the boundary between packaging and circuit boards, bringing significant changes to high-performance system architecture design.
WMCM: Another Path for Wafer-Level Multi-Chip Integration
In addition to the above technologies, **WMCM (Wafer-Level Multi-Chip Module)** is another packaging direction worth noting. This technology can be seen as a form of Wafer-Level Integration, representing a planar extension of traditional packaging.
WMCM no longer employs vertical chip stacking; instead, it integrates logic chips and memory on the same wafer plane, utilizing an RDL structure to replace the interposer. This design improves both thermal bottlenecks and signal latency while simplifying package thickness and cost.
Since all integration operations are completed at the wafer stage before dicing into individual chips, it enables a thinner, lighter, and more efficient multi-chip module structure.
From Packaging Innovation to System Integration
From CoWoS to CoPoS, and then to CoWoP and WMCM, it is evident that the core philosophy of packaging technology is shifting from “chip stacking” to “system integration.”
The emergence of different architectures reflects the industry’s diverse solutions to challenges such as performance, yield, heat dissipation, and cost. In the future, with the deepening of heterogeneous integration and chip partitioning, **Advanced Packaging will become the key technology to continue the spirit of Moore’s Law**.
Whoever can master the key materials, processes, and design capabilities in this packaging revolution will dominate the future of high-performance chips in the post-fab era.
Reference:
- Confused about CoWoS, CoPoS, and CoWoP? Which is the technology to watch for the next generation?
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